Analog Design Engineer (ZISPL Job No 633)

Analog Design Job Description:

Experience: 5 to 10 years

Candidate will have opportunities to design high performance transceivers along with critical analog functions, including:   

   • Analog-to-digital converters (ADC)   

   • Digital-to-analog converters (DAC)   

   • Phase-Locked Loop (PLL)   

   • Adaptive equalizers, finite-impulse response (FIR) filter, and decision-feedback equalizer (DFE)   

   • Serializer-Deserializer (Serdes)   

   • Clock and data recovery (CDR) circuits   

   • Timing critical circuits   

Designing high performance CMOS circuits in the following areas at a minimum:   

   • Bandgaps   

   • Regulators  

   • Bias circuits   

   • SCL circuits   

   • Amplifiers   

   • Oscillators   

   • DACs/ADCs   

Experience in filters and/or equalization, including but not limited to continuous time filter, discrete-time filters, FIR filter, and DFE, SerDes and timing circuits such as PLL, CDR, TX and RX functions is a plus. Preferred candidate is MSEE or PHD in EE with technical management experience in CMOS analog/mixed-signal integrated circuit design. Fluent in various CAD tools for analog design from RTL to layout (including circuit design, physical layout, extraction of design and verification) is a MUST. 

Key Description :

• Design and development of Analog or Mixed signal macros in cutting edge process technologies: mostly in 16nm/28nm/finfet
• Various phases of Analog design: transistor level design, circuit simulation, parasitic extraction, post layout simulations and layouts.
• Design and integration of analog/mixed-signal circuits 
• Most of the work will be on very high-speed design: 10/16 Gbps
• Understand the design of analog blocks used in PHY chips for high-speed communications: equalizer, PLL, CDR
• Experience with high frequency designs.